`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/18/2021 12:49:52 AM
// Design Name: 
// Module Name: flash_light
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module flash_light(
    input clk,
    input rst_n,
    input en,
    input key_value,
    input [3:0] work0,
    input [3:0] work1,
    input [3:0] rest0,
    input [3:0] rest1,
    output reg [3:0] dis0,
    output reg [3:0] dis1,
    output reg [3:0] dis2,
    output reg [3:0] dis3
    );
    reg [40:0] m;
    reg cout;
    initial m=30'b0;
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) m <=0;
        else if (m==50000001) m<=0;
        else  m <= m+1;
    end
    always@(posedge clk)
	begin
    if (key_value) 
        cout <= 0;
	else if(m==50000000) //可通过更
        cout <= ~ cout;
    else
        cout <= cout;
	end
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            dis0 <= 0;
            dis1 <= 0;
            dis2 <= 0;
            dis3 <= 0;
        end
        else if(en && cout==1) begin
                dis0 <= 10;
                dis1 <= 10;
                dis2 <= rest0;
                dis3 <= rest1;
            end
            
        else if (en==0 && cout==1) begin
            dis0 <= work0;
            dis1 <= work1;
            dis2 <= 10;
            dis3 <= 10;
        end
            else begin
                dis0 <= work0;
                dis1 <= work1;
                dis2 <= rest0;
                dis3 <= rest1;
            end
        end

endmodule
